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DATA SHEET
74HCT7273 Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
Product specification File under Integrated Circuits, IC06 1999 Oct 01
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
FEATURES * ESD protection: HBM EIA/JESD22-A114-A Exceeds 2000 V MM EIA/JESD22-A115-A Exceeds 200 V * Ideal buffer for MOS microprocessor or memory * Eight positive edge-triggered D-type flip-flops * Common clock and master reset * Output capability: standard (open drain) * ICC category: MSI. DESCRIPTION
74HCT7273
The 74HCT7273 is a high-speed SI-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no 7A. The 74HCT7273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. A LOW level on the MR input forces all outputs LOW, independently of the clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. The 74HCT7273 has open-drain N-outputs, which are clamped by a diode connected to VCC. When a HIGH is clocked in the flip-flop, the output comes in the high-impedance OFF-state. The output may now be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and OR-tied output applications, the device must have a pull-up resistor to establish a logic HIGH level.
QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 C; tr = tf = 6.0 ns. SYMBOL tPZL/tPLZ CP to Qn MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) + (V02/RL) x duty factor LOW where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; RL = pull-up resistor in M; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC - 1.5 V. maximum clock frequency input capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 PARAMETER propagation delay CONDITIONS CL = 50 pF; VCC = 4.5 V 16 23 56 3.5 37 ns ns MHz pF pF TYPICAL UNIT
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
FUNCTION TABLE See note 1. INPUTS OPERATING MODES MR Reset (clear) Load `1' Load `0' Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level. l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; X = don't care; = LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE OUTSIDE NORTH AMERICA 74HCT7273D 74HCT7273N NORTH AMERICA 74HCT7273D 74HCT7273N TEMPERATURE RANGE -40 to +125 C PINS 20 20 PACKAGE SO DIP L H H CP X Dn X h l
74HCT7273
OUTPUTS Qn L Z L
MATERIAL plastic plastic
CODE SOT163-1 SOT146-1
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
PINNING PIN 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 MR Q0 to Q7 D0 to D7 GND CP VCC SYMBOL flip-flop outputs data inputs ground (0 V) DESCRIPTION asynchronous master reset (active LOW)
74HCT7273
clock input (LOW-to-HIGH, edge triggered) DC supply voltage
handbook, halfpage
MR 1 Q0 2 D0 3 D1 4 Q1 5
20 VCC 19 Q7 18 D7 17 D6 16 Q6 11 1 CP MR Q0 2
handbook, halfpage
3 D0
4 D1
7 D2
8 D3
13 D4
14 D5
17 D6
18 D7
7273
Q2 6 D2 7 D3 8 Q3 9 GND 10
MNA380
15 Q5 14 D5 13 D4 12 Q4 11 CP
Q1 5
Q2 6
Q3 9
Q4 12
Q5 15
Q6 16
Q7 19
MNA381
Fig.1 Pin configuration.
Fig.2 Logic symbol.
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
74HCT7273
handbook, halfpage
11 1
C1 R 2 5 6 9 12 15 16 19
MNA382
3 4 7 8 13 14 17 18
1D
Fig.3 IEC logic symbol.
3 handbook, full pagewidth D0 D Q FF1 CP RD 11 1 CP MR
4 D1 D Q FF2 CP RD
7 D2 D Q FF3 CP RD
8 D3 D Q FF4 CP RD
13 D4 D Q FF5 CP RD
14 D5 D Q FF6 CP RD
17 D6 D Q FF7 CP RD
18 D7 D Q FF8 CP RD
Q0 2 5
Q1 6
Q2 9
Q3
Q4 12
Q5 15
Q6 16
Q7 19
MNA383
Fig.4 Functional diagram.
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D0 D1 D2 D3 D Q FF1 CP RD D Q FF2 CP RD D Q FF3 CP RD D
Philips Semiconductors
FF4 CP RD
handbook, full pagewidth
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
D4
D5
D6
D7
Q
D
Q FF5
D
Q FF6
D
Q FF7
D
Q FF8
CP RD
CP RD
CP RD
CP RD
6
CP MR VCC VCC VCC VCC VCC VCC VCC VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA384
Product specification
74HCT7273
Fig.5 Logic diagram.
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
RECOMMENDED OPERATING CONDITIONS
74HCT7273
TYPE SYMBOL VCC VI VO Tamb tr,tf (t/f) PARAMETER DC supply voltage input voltage output voltage operating ambient temperature input rise and fall times except for Schmitt-trigger inputs see DC and AC characteristics per device VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CONDITIONS MIN. 4.5 0 0 -40 -40 - - - - - - - 6.0 6.0 6.0 TYP. 5.0 MAX. 5.5 VCC VCC +85 +125 500 500 500 V V V C C ns/V UNIT
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VO IIK IOK IO ICC Tstg PD PARAMETER DC supply voltage output voltage DC input diode current DC output diode current DC output source or sink current DC VCC or GND current storage temperature power dissipation per package plastic DIP plastic mini-pack (SO) Note 1. For DIP package: above 70 C the value of PD derates linearly with 12 mW/K. 2. For SO package: above 70 C the value of PD derates linearly with 8 mW/K. for temperature range: -40 to +125 C note 1 note 2 - - 750 500 mW mW VI < -0.5 V or VI > VCC + 0.5 V VO < -0.5 V or VO > VCC + 0.5 V -0.5V < VO < VCC + 0.5 V CONDITIONS MIN. -0.5 -0.5 - - - - -65 MAX. +7.0 +7.0 20 20 25 50 +150 UNIT V V mA mA mA mA C
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL; IO = 20 A VI = VIH or VIL; IO = 4.0 mA II IOZ input leakage current HIGH level output leakage current VI = VIH or VIL VI = VIL; VO = VCC or GND VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 5.5 4.5 to 5.5 25 - 0.8 0.1 Tamb (C) -40 to +85 - 0.8 0.1 0.33 1.0 5.0
74HCT7273
-40 to +125 UNIT - 0.8 0.1 0.4 1.0
MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 - - - - - 1.6 1.2 0 2.0 - - - - - 2.0 - - - - - V V V V A
0.15 0.26 - - 0.1 0.5
10.0 A
ICC ICC
quiescent supply VI = VCC or GND; current IO = 0 additional quiescent supply current per input pin VI = VCC - 2.1 V other inputs at VCC or GND; IO = 0; note 1
5.5 4.5 to 5.5
- -
- 100
8.0 360
- -
80 450
- -
160 490
A A
Note 1. The value off additional quiescent supply current (ICC) for a unit load of 1 is given in the specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in Table 1. Table 1 INPUT MR CP Dn UNIT LOAD COEFFICIENT 1.50 1.50 0.40
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
AC CHARACTERISTICS Ground = 0 V; tr = tf 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPZL/tPLZ tPZL tTHL tTLH tW tW trem tsu th fmax VCC (V) - - - - 16 16 10 12 3 30 25 MIN. TYP. MAX. 16 23 7 - 9 8 -2 5 -4 56 30 34 15 110 - - - - - - Tamb (C) -40 to +85 MIN. MAX. - - - - 20 20 13 15 3 24 38 43 19 110 - - - - - -
74HCT7273
-40 to +125 MIN. - - - - 24 24 15 18 3 20 MAX. 45 51 22 110 - - - - - -
UNIT
propagation delay see Figs 6 and 9 4.5 CP to Qn propagation delay see Figs 6 and 9 4.5 MR to Qn output transition time output transition time clock pulse width HIGH or LOW see Figs 6 and 9 4.5 see Figs 7 and 9 4.5 see Figs 6 and 9 4.5
ns ns ns ns ns ns ns ns ns MHz
master reset see Figs 7 and 9 4.5 pulse width; LOW removal time MR to CP set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency see Figs 7 and 9 4.5 see Figs 8 and 9 4.5 see Figs 8 and 9 4.5 see Figs 6 and 9 4.5
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
AC WAVEFORMS
74HCT7273
handbook, full pagewidth
1/fmax VI CP input GND tW t PZL VOH Qn output VOL 90% VM 10% t THL 10%
MNA385
VM
t PLZ
VM = 1.3 V; VI = GND to 3 V.
Fig.6
The clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and maximum clock pulse frequency.
handbook, full pagewidth
VCC MR input GND tW VCC CP input GND t PHL VOH Qn output VOL VM 10%
MNA386
VM
t rem
VM
t TLH 90%
VM = 1.3 V; VI = GND to 3 V.
Fig.7
Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP).
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
74HCT7273
handbook, full pagewidth
VI CP input GND t su th VI Dn input GND VM t su th VM
VOH Q n output VOL
MNA387
VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig.8 Data set-up and hold times for the data input (Dn).
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL
MNA219
VO
1000
VCC open GND
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH VCC
S1 open GND
Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter "AC characteristics"). RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.9 Load circuit for switching times.
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm
74HCT7273
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
74HCT7273
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-05-24
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Manual soldering
74HCT7273
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable
74HCT7273
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note suitable suitable(1)
74HCT7273
WAVE
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
NOTES
74HCT7273
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
NOTES
74HCT7273
1999 Oct 01
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive edge-trigger; open drain outputs
NOTES
74HCT7273
1999 Oct 01
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Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/01/pp20
Date of release: 1999
Oct 01
Document order number:
9397 750 05733

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